Separators for handling, transporting, or storing semiconductor wafers

ABSTRACT

Introduced here is a wafer separator configured to carry a semiconductor wafer with improved efficiency, protection, and reduced costs when utilized in the handling, transport, or storage of semiconductor components. The wafer separator may include a circular ring having an outer edge defining a periphery of the circular ring. The circular ring may include an inner edge defining a central opening of the circular ring. The wafer separator may include a first-right angled recess for receiving a semiconductor wafer that extends downward from a top surface of the circular ring. The wafer separator may also include a second right-angled recess for maintaining a gap beneath the semiconductor wafer when the semiconductor wafer is set within the first right-angled recess. In some embodiments, the wafer separator also includes interlock components for connecting the wafer separator to adjacent wafer separators.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. Provisional Application No.62/551,766, titled “Separators for Handling, Transporting, or StoringSemiconductor Wafers” and filed on Aug. 29, 2017, which is incorporatedby reference herein in its entirety.

RELATED FIELD

The present technology generally relates to separators for protectingsemiconductor components and, more specifically, to separators designedto protect semiconductor wafers while maintaining minimal contact withthe semiconductor wafers.

BACKGROUND

Different configurations can be used to facilitate the handling,transport, and storage of semiconductor components, such assemiconductor wafers, semiconductor dies, etc. For example,manufacturers must often transport semiconductor components to variousfacilities to complete a semiconductor wafer manufacturing process andto manufacture integrated circuits from the semiconductor wafers.

One configuration to facilitate the handling, transport, and storage ofsemiconductor components may be utilizing an injection-molded tray.Injection-molded trays are used to restrict the movement ofsemiconductor components during transport to various testing andmanufacturing facilities. The injection-molded trays may be designedspecifically to contain and protect, for example, semiconductor wafers,which are generally thin and circular. Conventional injection-moldedtrays restrict the movement of the semiconductor components duringtransport by maintaining physical contact with the semiconductorcomponents.

However, conventional injection-molded trays exhibit several limitationson providing adequate protection to sensitive semiconductor components.For example, conventional injection-molded trays may inadvertentlydamage a semiconductor component due to an external force that isapplied to part(s) of the injection-molded tray in contact with thesemiconductor component. The injection-molded trays may also fail toproperly dissipate static electricity, which may lead to damage to thesemiconductor component due to electrostatic discharge (ESD). Suchlimitations may lead to damaged semiconductor components, greatertransport costs, and low efficiency of semiconductor wafer manufacturingand testing.

BRIEF DESCRIPTION OF THE DRAWINGS

Various features of the technology will become more apparent to thoseskilled in the art from a study of the Detailed Description inconjunction with the drawings. Embodiments of the technology areillustrated by way of example and not limitation in the drawings, inwhich like references may indicate similar elements.

FIG. 1 is a cross-sectional, perspective view of a semiconductor waferseparator (also referred to more simply as “wafer separators” or“separators”) designed to hold a semiconductor wafer.

FIG. 2 is a top section view of the semiconductor wafer separator.

FIG. 3 is a cross-sectional view of the semiconductor wafer separatorholding a semiconductor wafer.

FIG. 4 is a cross-sectional view of multiple semiconductor waferseparators holding semiconductor wafers.

FIG. 5 is an exploded view of multiple semiconductor wafer separatorsand semiconductor wafers stacked for handling, transport, and/or storageof the multiple semiconductor wafers.

FIG. 6 depicts an example method of handling a semiconductor wafer usinga semiconductor wafer separator.

The drawings depict various embodiments for the purpose of illustrationonly. Those skilled in the art will recognize that alternativeembodiments may be employed without departing from the principles of thetechnology. Accordingly, while specific embodiments are shown in thedrawings, the technology is amenable to various modifications.

DETAILED DESCRIPTION

Semiconductor component separators may carry semiconductor componentsand protect the semiconductor components from physical damage. Examplesof semiconductors components include semiconductor wafers, semiconductordies (e.g., bumped die or bare die), and other electronic componentsused in the fabrication of integrated circuits (ICs). Certainembodiments have been described in the context of semiconductor wafersfor the purpose of illustration only. Those skilled in the art willrecognize the separators introduced here could be used in the handling,transport, and/or storage of any type of semiconductor component.

Semiconductor wafer separators may be utilized to transportsemiconductor wafers between multiple facilities during thesemiconductor manufacturing and testing processes. Moreover,semiconductor wafer separators may be utilized to store semiconductorwafers within a storage facility before, during, or after suchprocesses. Semiconductor wafer separators prevent semiconductor wafersfrom coming into contact with one another, thereby preventing damage tothe semiconductor wafers. Semiconductor wafer separators may be used topresent the semiconductor wafer to a manual placement tool or anautomatic placement tool (also referred to as a “pick-and-placemachine”) for testing, wafer dicing, etc. Wafer dicing may dice thesemiconductor wafer, and utilize a portion of the semiconductor wafer inthe fabrication of an integrated circuit.

Semiconductor wafer separators can be used in the semiconductor industryin the transport of semiconductor wafers because semiconductor waferseparators reliably protect the semiconductor wafers from damage duringtransport. However, conventional semiconductor wafer separators sufferfrom several drawbacks. For example, many designs place the separator indirect contact with a large portion of the semiconductor wafer, whichincreases the risks of damage to the semiconductor wafer from physicalcontact and electrostatic discharge.

Introduced here, therefore, are semiconductor wafer separators thatimprove reliability in protecting the semiconductor wafers duringhandling, transport, and storage throughout various manufacturing and/ortesting processes. The semiconductor wafer separator may include a firstright-angled recess to receive a semiconductor wafer. The firstright-angled recess is designed such that it has a specified width/depththat limits the portion of the semiconductor wafer in contact with theseparator. The semiconductor wafer separator may also include a secondright-angled recess to maintain a gap beneath the semiconductor waferand prevent physical damage to the underside of the semiconductor wafer.

Terminology

References in this description to “an embodiment” or “one embodiment”means that the particular feature, function, structure, orcharacteristic being described is included in at least one embodiment.Occurrences of such phrases do not necessarily refer to the sameembodiment, nor are they necessarily referring to alternativeembodiments that are mutually exclusive of one another.

Unless the context clearly requires otherwise, the words “comprise” andcomprising” are to be construed in an inclusive sense rather than anexclusive or exhaustive sense (i.e., in the sense of “including but notlimited to”). The terms “connected,” “coupled,” or any variant thereofis intended to include any connection or coupling, either direct orindirect, between two or more elements. The coupling/connection can bephysical, logical, or a combination thereof. For example, two devicesmay be physically, electrically, and/or communicatively coupled to oneanother.

When used in reference to a list of multiple items, the word “or” isintended to cover all of the following interpretations: any of the itemsin the list, all of the items in the list, and any combination of itemsin the list.

Technology Overview

FIG. 1 is a cross-sectional, perspective view of a semiconductor waferseparator 100 (also referred to more simply as “wafer separators” or“separators”) designed to hold a semiconductor wafer. As furtherdescribed below, the semiconductor wafer separator 100 may be configuredto handle semiconductor wafers of different sizes (e.g., wafers having avariety of diameters from 25.4 mm (1 inch) to 300 mm (11.8 inches)) toaccommodate different semiconductor fabrication plants (also referred toas “fabs”), processes, etc. The semiconductor wafer separator 100 may beconfigured to maintain minimal contact with the semiconductor wafer toprevent damage to the semiconductor wafer.

In some embodiments, the wafer separator 100 includes a circular body110 whose shape is substantially similar to that of the semiconductorwafer. The shape and/or size of the circular body 110 may correspond tothe conventional circular shape of many semiconductor wafers. In otherembodiments, the wafer separator 100 includes a noncircular body (thoughthe cavity within which the semiconductor wafer is set may still becircular). The size and/or shape of the structural body of the waferseparator 100 may be based on the design of the container within whichthe wafer separator 100 is to be placed. For example, circular bodiesmay be used in combination with a cylindrical container, whilenoncircular bodies may be used in combination with a non-cylindricalcontainer (e.g., a cuboid or a triangular prism).

In some embodiments, the circular body 110 takes the form of an annulushaving an outer edge 112 defining the periphery of the circular body 110and an inner edge 114 defining a central opening 116 of the circularbody. The outer edge 112 may extend along the entire outer periphery ofthe circular body 110 in an uninterrupted manner. The inner edge 114,meanwhile, may be substantially parallel to the outer edge 112.Accordingly, when the semiconductor wafer is set within the circularbody 110, the inner edge 114 may be substantially perpendicular to thebottom surface of the semiconductor wafer and substantially parallel tothe outer edge of the semiconductor wafer. In some embodiments thesidewalls forming the inner edge 114 are substantially orthogonal to theundersign of the circular body 110, while in other embodiments thesidewalls forming the inner edge are pitched (i.e., angled). The centralopening 116 may be arranged such that it is centered at the center ofthe semiconductor wafer separator 100 and/or the center of thesemiconductor wafer.

The circular body 110 may include a top surface 118 and a bottom surface120. The top surface 118 and the bottom surface 120 may be substantiallyparallel to one another, as well as substantially perpendicular to theouter edge 112. The top surface 118 may define the uppermost point(i.e., the greatest height of any surface) of the circular body 110. Insome embodiments the bottom surface 120 defines the lowermost point ofthe circular body 110, while in other embodiments one or more interlockcomponents disposed along the bottom surface 120 define the lowermostpoint(s).

A first right-angled recess 122 formed in the circular body 110 may beadapted to receive the semiconductor wafer. The first right-angledrecess 122 may extend downward from the top surface 118. In someembodiments, the first right-angled recess 122 forms an angle thatmeasures substantially 90 degrees and complements the form of thesemiconductor wafer. Accordingly, the first right-angled recess 122 maycomprise a first vertical surface 124 and a first horizontal surface 126that are orthogonal to one another. The first vertical surface 124 maybe substantially parallel with the outer edge 112, while the firsthorizontal surface 126 may be substantially parallel with the topsurface 118. A semiconductor wafer may be in contact with the firsthorizontal surface 126 and/or the first vertical surface 124 when thesemiconductor wafer is placed in the first right-angled recess 122.

Those skilled in the art will recognize that the first right-angledrecess 122 could also form some other angle (i.e., other thansubstantially 90 degrees). For example, the first right-angled recess122 may instead include a first horizontal surface 24 and/or a firstvertical surface 126 that is curved. Curving the first vertical surface24 of the first right-angled recess 122 may allow for less surface areaof the first vertical surface 124 to be in contact with a semiconductorcomponent. Additionally or alternatively, the first vertical surface 124may include a pocket or a slot that allows the outer portion of thesemiconductor wafer to fit into the first right-angled recess 122 andprevents vertical movement of the semiconductor wafer.

The circular body 110 may also include a second right-angled recess 128that extends downward from the first horizontal surface 126 of the firstright-angled recess 122. However, the second right-angled recess 128 maynot come into contact with the semiconductor wafer. As illustrated inFIG. 3, the second right-angled recess 128 may cause a gap to be formedbeneath the semiconductor wafer. More specifically, a second verticalsurface 144 may ensure that a gap of a specific height is formed betweenthe semiconductor wafer and the second horizontal surface 142 of thesecond right-angled recess 128. The second right-angled recess 128 mayinclude an angle substantially similar to that of the first right-angledrecess 122.

A first interlock component 132 may be located on the circular body 110of the semiconductor wafer separator 100. Here, for example, the firstinterlock component 132 is disposed along the top surface 118 of thecircular body 110. The first interlock component 132 may be designed toengage with another interlock component.

A second interlock component 134 may also be located on the circularbody 110 of the semiconductor wafer separator 100. Here, for example,the second interlock component 134 is disposed along the bottom surface120 of the circular body 110.

The interlock components may be of various interlock types (e.g.,complementary interlock types). For instance, one of the interlockcomponents may comprise a first interlock component type, such as anotch, slot, recess, or another known form/component capable of receivean interlock component. Meanwhile, the other interlock component maycomprise a second interlock component type, such as a protrusion,projection, or another known form/component capable of being received byan interlock component of the first interlock component type. The firstcomponent type and the second component type may be disposed at an anglerelative to the outer edge 112.

The second interlock component 134 may comprise a different interlockcomponent type than the first interlock component 132. Here, forexample, the first interlock component 132 comprises a first interlockcomponent type (e.g., a notch) and the second interlock component 134comprises a second interlock component type (e.g., a protrusion).Accordingly, the first interlock component 132 can engage acorresponding interlock component of the second type on anupwardly-adjacent wafer separator, while the second interlock component134 can engage a corresponding interlock component of the first type ona downwardly-adjacent wafer separator. The interlock components 132, 134could be of the same interlock component type or different interlockcomponent types.

While the interlock components of FIG. 1 extend around the entirety ofthe top and bottom surfaces 118, 120, those skilled in the art willrecognize that other designs are also possible. More specifically, thetop and bottom surfaces 118, 120 may each include a specified number(e.g., two, three, four, or eight) of interlock components. For example,the circular body 110 could include two interlock components on oppositesides of the top surface 118 and two interlock components on oppositesides of the bottom surface 120. As another example, the circular body110 could include four interlock components equally distributed alongthe top surface 118 and four interlock components equally distributedalong the bottom surface 120. The number of interlock componentsdisposed along the top and bottom surfaces 118, 120 are generally thesame to allow for easy stacking.

FIG. 2 is a top section view of the semiconductor wafer separator 200.The wafer separator 2 of FIG. 2 may be substantially similar to thewafer separator 100 of FIG. 1. As noted above, the first right-angledrecess 222 and the second right-angled recess 228 may continuouslyextend along the periphery of the circular body 210. Alternatively, thefirst right-angled recess 222 may include a notch 238. The notch 238represents an area (i.e., a break) where the first right-angled recess222 does not extend along the periphery of the circular body 210. Thenotch 238 causes less of the first horizontal surface 226 of the firstright-angled recess 222 to be in contact with the semiconductor wafer,while still allowing the first vertical surface 224 of the firstright-angled recess 222 to prevent the semiconductor wafer from movinglaterally.

The notch 238 may also allow for the semiconductor wafer to be removedfrom the circular body 210. More specifically, the notch 238 canpartially or entirely extend through the circular body 210, therebyallowing the semiconductor wafer to be readily removed from the waferseparator 200 either manually or automatically (e.g., by acomputer-implemented system, such as a pick-and-place robotic system).In some embodiments, the circular body 210 includes multiple notches238. The notches 238 may be located equidistant around the periphery ofthe circular body 210.

The semiconductor wafer separator 200 may include a carrier component240. The carrier component 240, which may comprise an outer portion ofthe circular body 210, can be configured to allow the wafer separator200 to be easily transported. The carrier component 240 may be engagedto the outer edge 212 of the circular body 210. In some embodiments, thecarrier component 240 is configured to allow for the wafer separator 200and other wafer separators that are engaged to one another to betransported together with greater efficiency. The carrier component 240may comprise a shape that may be easily transported, such as asubstantially square, rectangular, or another known shape. In someembodiments the carrier component 240 is separately engaged to thecircular body 210, while in other embodiments the wafer separator 200 isa single piece including the circular body 210 and the carrier component240. The carrier component 240 may include handles, latches, or otherknown components to assist in the transport of the wafer separator 200.

FIG. 3 is a cross-sectional view of the semiconductor wafer separator300 holding a semiconductor wafer 330. The wafer separator as describedin FIG. 3 may be substantially similar to the wafer separator in FIG. 1and FIG. 2. The semiconductor wafer 330 may be set in the firstright-angled recess 322 of the circular body 310. The first right-angledrecess 322 maintains contact with the semiconductor wafer 330 duringhandling, transport, storage, etc., and prevents the semiconductor wafer330 from moving in various directions.

The height of the top surface 318 may be substantially similar to orequal to the height of the semiconductor wafer 330 when thesemiconductor wafer 330 is set in the first right-angled recess 322.That is, the top surface 318 may be in line with the top surface of thesemiconductor wafer 330. In some embodiments, the top surface 318 may beabove than the top surface of the semiconductor wafer 330, which causesa space to be formed between the semiconductor wafer 330 and anupwardly-adjacent wafer separator.

The first right-angled recess 322 may prevent the semiconductor wafer330 from coming into contact with another semiconductor wafer or someother external object. More specifically, the first right-angled recess322 can come into contact with the outer portion of the semiconductorwafer 330, while allowing for the majority of the inner portion of thesemiconductor wafer 330 to not be in contact with the circular body 310.Minimizing contact between the semiconductor wafer 330 and the circularbody 310 may improve effectiveness in protecting the semiconductor fromdamage due to external forces and/or ESD. Accordingly, some embodimentsof the semiconductor wafer separator 300 maximize the diameter of thecentral opening 316 by minimizing the depth/width of the firstright-angled recess 322 and/or the second right-angled recess 328 (whilestill ensuring that the semiconductor wafer 330 can stably sit withinthe first right-angled recess 322).

The second right-angled recess 328 may be configured to maintain a gap336 beneath the semiconductor wafer 330 when the semiconductor wafer 330is set within the first right-angled recess 322. The second right-angledrecess 328 may have a second vertical surface of a specified height thatensures the gap 336 is of the specified height. In some embodiments thesecond right-angled recess 328 creates the gap 336 between the bottomsurface of the semiconductor wafer 330 and the second horizontal surface342 of the second right-angled recess 328, while in other embodimentsthe second right-angled recess 328 created the gap between the bottomsurface of the semiconductor wafer 330 and the top surface of adownwardly-adjacent semiconductor wafer. The gap 336 may assist inpreventing damage to the inner portion of the semiconductor wafer 330.The inclusion of spaces and gaps, such as gap 336, provides an air gapbetween the semiconductor wafer 330 and the wafer separator 300. Airgaps may assist in preventing the collection of static electricity anddamage from electrostatic discharge onto the semiconductor wafer 330.The air gaps may also assist in preventing damage to the semiconductorwafer 330.

FIG. 4 is a cross-sectional view of multiple stacked semiconductor waferseparators holding semiconductor wafers. The wafer separators 400, 450may be substantially similar to the wafer separator as described in FIG.1, FIG. 2, and FIG. 3. Here, for example, the wafer separator 400 isengaged to a downwardly-adjacent wafer separator 450. Each waferseparator may be configured to engage with adjacent wafer separators,including downwardly-adjacent wafer separators and upwardly-adjacentwafer separators.

The wafer separator 400 may include a first interlock component 432 anda second interlock component 434. For example, the interlock components432, 434 of the wafer separator 400 may be configured to engage withinterlock components of an adjacent wafer separator. As shown in FIG. 4,the second interlock component 434 of the wafer separator 400 may engagea first interlock component 452 of the downwardly-adjacent waferseparator 450. The second interlock component 434 of the wafer separator400 may comprise a protrusion, and the first interlock component 452 ofthe downwardly-adjacent wafer separator 450 may comprise a recess.Similarly, the first interlock component 432 of the wafer separator 400may be a recess adapted to engage with a second interlock component ofan upwardly-adjacent wafer separator (not shown).

The wafer separator 400 may receive a semiconductor wafer 430, and thedownwardly-adjacent wafer separator 450 may receive a secondsemiconductor wafer 456. In some embodiments a space exists between thebottom surface 420 of the wafer separator 400 and the top surface of thesecond semiconductor wafer 456, while in order embodiments the bottomsurface 420 of the wafer separator 400 is directly adjacent to the topsurface of the second semiconductor wafer 456.

In some embodiments, a wafer separator securing component 460 is used tofurther secure and lock the wafer separator 400 to another waferseparator, such as the downwardly-adjacent wafer separator 450. Thewafer separator securing component 460 may include a slot, latch, orother known locking component disposed on the outer edge 412 of thewafer separator 400. The wafer separator securing component 460 may bealigned and secured to a complementary securing component on thedownwardly-adjacent wafer separator 450. Wafer separator securingcomponents 460 could be used to secure the wafer separator 400 to anyadjacent wafer separator (e.g., an upwardly-adjacent wafer separatorand/or a downwardly-adjacent wafer separator).

The wafer separator securing component 460 may comprise multiplecomponents configured to secure the wafer separators 400, 450 togetherusing a known locking mechanism. For example, the wafer separatorsecuring component 460 can include a locking component configured tolock the wafer separator 400 to the downwardly-adjacent wafer separator450. Such a design reliably prevents independent movement of eitherwafer separator 400, 450 and prevents damage to the semiconductor wafers430, 456 during transport.

FIG. 5 is an exploded view of multiple semiconductor wafer separators1A-F and semiconductor wafers 30A-E stacked for handling, transport,and/or storage of the multiple semiconductor wafers 30A-E.

As illustrated in FIG. 5, multiple wafer separators 1A-F may be used toseparately retain multiple semiconductor wafers 30A-E. The multiplewafer separators 1A-F may be stacked together to allow for thesimultaneous transport of multiple semiconductor wafers 30A-E.Transporting multiple semiconductor wafers 30A-E simultaneously mayincrease efficiency in transport and the manufacture of semiconductorwafers 30A-E and integrated circuits (ICs).

The circular body of each wafer separator may be configured to engagewith an adjacent wafer separator. In some embodiments, the carriercomponent (e.g., carrier component 240 of FIG. 2) of each waferseparator may be stacked. The carrier components may allow for the waferseparators 1A-F to be stacked and transported with greater efficiency.The carrier components may be configured to fit in a conventionaltransport size.

To provide further protection of the semiconductor wafers 30 duringtransport, one or more protective substrates 62A, 62B may be utilized.The protective substrates 62A, 62B may comprise a lightweight, resilientmaterial, such as polyethylene foam. Other known material could also beused to protect the fragile semiconductor wafers 30A-E. The protectivesubstrate 62A, 62B may be resistive to moisture and/or electricity toprevent static electricity collection and electrostatic discharge. Theprotective substrate 62A, 62B may comprise an anti-static material thatprevents the buildup of static electricity.

In some embodiments, a first protective substrate 62A is disposedbetween the top cover 64 and the uppermost wafer separator 1A-F and asecond protective substrate 62B may be disposed between the bottom cover66 and the lowermost wafer separator 1A-F. Moreover, one or moreprotective substrates 62A, 62B could be disposed between each pair ofthe wafer separators to provide additional protection from damage andelectrostatic discharge. A protective substrate may be configured to bedisposed within one or both of the covers 64, 66. The protectivesubstrate 62A, 62B may engage a given wafer separator, for example, byengaging the interlock components of the given wafer separator.

A top cover 64 may be disposed above the wafer separators 1A-F. The topcover 64 may be an additional protective component to protect thesemiconductor wafers 30 during transport. The top cover 64 may protectthe wafer separators 1A-F and semiconductor wafers 30A-E from damage dueto external forces applied from above (e.g., to the top cover 64). Thetop cover 64 may be configured to be placed over one or more waferseparators 1A-E stacked together. The top cover 64 may engage theuppermost wafer separator (or another of the wafer separators), forexample, by engaging an interlock component of the uppermost waferseparator. Additionally or alternatively, the top cover 64 can engagethe wafer separator securing component of the uppermost wafer separator(or another of the wafer separators).

A bottom cover 66 may be disposed below the wafer separators 1A-F. Thebottom cover 66 may have substantially similar qualities as the topcover 64. The top cover 64 may engage the bottom cover 66, which maycover some or all of the wafer separators 1A-F and the semiconductorwafers 30A-E. The top cover 64 and bottom cover 66 may prevent moisturefrom contacting the semiconductor wafers 30A-E.

Any of the wafer separators 1A-F, top cover 64, and bottom cover 66 maycomprise a known material suitable for injection molding. For example,the wafer separator 1A-F may be composed of an anti-static orstatic-dissipative material. As another example, the wafer separator1A-F may be composed of a resilient material able to protect thesemiconductor wafers 30A-E from physical damage. The material of any ofthe wafer separator 1A-F, top cover 64, and bottom cover 66 may comprisepolyethylene thermoplastic, ethylene chlorotrifluoroethylene (ECTFE), orany other material used in the semiconductor industry to createinjection-molded trays or wafer separators. In some embodiments, thewafer separators 1A-F comprise at least two materials, including a firstresilient material to avoid physical damage and a second anti-static ornon-conductive material. The second material may be sprayed onto thefirst material, adhered to the first material, or incorporated into thefirst material (e.g., during the manufacturing process).

Another object of the present technology introduced here is to providetechniques to safely carry, transport, and remove a semiconductor waferfrom a semiconductor wafer separator. FIG. 6 depicts an example method600 of handling a semiconductor wafer using a semiconductor waferseparator.

A manufacturer or some other entity involved in the semiconductor wafermanufacturing and transportation process may receive a wafer separator(step 601). The wafer separator can include a circular ring thatincludes an outer edge defining a periphery of the wafer separator. Thecircular ring may also include an inner edge defining a central opening.The wafer separator (e.g. the wafer separator 100 in FIG. 1) can includea first right-angled recess extending downward from a top surface of thecircular ring and a second right-angled recess configured to maintain agap beneath a semiconductor wafer set within the first right-angledrecess.

The semiconductor wafer can then be placed within the wafer separator(step 602). As illustrated in FIG. 3, the semiconductor wafer may beplaced within the first right-angled recess of the wafer separator.Placing the semiconductor wafer within the first right-angled recess ofthe wafer separator allows the wafer separator to restrict movement ofthe semiconductor wafer while maintaining minimal contact with thesemiconductor wafer.

In some embodiments, a protrusion on the wafer separator engages arecess of an adjacent wafer separator (step 603). For example, the waferseparator may engage an upwardly-adjacent wafer separator and/or adownwardly-adjacent wafer separator. A protrusion on the outer surfaceof the wafer separator can engage a recess disposed along the outersurface of the adjacent wafer separator (e.g., a downwardly-adjacentwafer separator). Moreover, a recess disposed along the outer surface ofthe wafer separator can engage a protrusion disposed along the outersurface of another adjacent wafer separator (e.g., an upwardly-adjacentwafer separator). Thus, the wafer separator may include different typesof interlock component. Each interlock component may be configured toengage with a corresponding interlock component on an adjacent waferseparator.

The semiconductor wafer may be removed from the wafer separator by aplurality of notches along the wafer separator (step 604). For example,a manual or automatic tool may be configured to pick up thesemiconductor wafer from the wafer separator. The plurality of notcheson the wafer separator may be utilized to safely and efficiently removethe semiconductor wafer from the wafer separator without damaging thesemiconductor wafer or the wafer separator (which may be reused multipletimes). The plurality of notches may be located equidistant around theperiphery of the circular body of the wafer separator.

Unless contrary to physical possibility, it is envisioned that the stepsdescribed above may be performed in various sequences and combinations.Additional steps could also be included in some embodiments. Forexample, the manufacturer/packager (or some other entity) could vacuumseal the wafer separator(s) or perform some other technique for reducingthe likelihood of damage from ESD.

Although some embodiments are described in the context of certainsemiconductor components (e.g., semiconductor wafers or semiconductordies), those skilled in the art will readily appreciate that thetechnology can be used to secure other electronic components as well.

Remarks

The foregoing examples of various embodiments have been provided for thepurposes of illustration and description. These examples are notintended to be exhaustive. Many variations will be apparent to oneskilled in the art. Certain embodiments were chosen in order to bestdescribe the principles of the technology introduced herein, therebyenabling others skilled in the relevant art to understand the claimedsubject matter, the various embodiments, and the variations that may besuited to particular uses.

The language used in the specification has been principally selected forreadability and instructional purposes. It may not have been selected todelineate or circumscribe the subject matter. Therefore, it is intendedthat the scope of the technology be limited not by this specification,but rather by any claims that issue based hereon. Accordingly, thedisclosure of the technology is intended to be illustrative (rather thanlimiting) of the scope of the technology, which is set forth in thefollowing claims.

What is claimed is:
 1. A semiconductor wafer separator, comprising: acircular ring including: an outer edge defining a periphery of thecircular ring, and an inner edge defining a central opening of thecircular ring; a first right-angled recess configured to receive asemiconductor wafer, wherein the first right-angled recess extendsdownward from a top surface of the circular ring; and a secondright-angled recess configured to maintain a gap beneath thesemiconductor wafer when the semiconductor wafer is set within the firstright-angled recess.
 2. The semiconductor wafer separator of claim 1,further comprising: a first interlock component disposed along the topsurface of the circular ring; and a second interlock component disposedalong a bottom surface of the circular ring.
 3. The semiconductor waferseparator of claim 2, wherein the first interlock component is a recessadapted to engage a corresponding second interlock component of anupwardly-adjacent wafer separator.
 4. The semiconductor wafer separatorof claim 2, wherein the second interlock component is a protrusionadapted to engage a corresponding first interlock component of adownwardly-adjacent wafer separator.
 5. The semiconductor waferseparator of claim 1, wherein the top surface of the circular ring issubstantially coplanar with a top surface of the semiconductor waferwhen the semiconductor wafer is set within the first right-angledrecess.
 6. The semiconductor wafer separator of claim 2, furthercomprising: a wafer separator securing component configured to securethe semiconductor wafer separator to an upwardly-adjacent waferseparator.
 7. The semiconductor wafer separator of claim 1, wherein thefirst right-angled recess comprises a notch configured to facilitate theremoval of the semiconductor wafer from the circular ring when thesemiconductor wafer is set within the first right-angled recess.
 8. Thesemiconductor wafer separator of claim 1, wherein the first right-angledrecess comprises a plurality of notches disposed equidistant along theperiphery of the circular ring, and wherein the plurality of notches areconfigured to facilitate the removal of the semiconductor wafer from thecircular ring when the semiconductor wafer is set within the firstright-angled recess.
 9. The semiconductor wafer separator of claim 4,further comprising: the semiconductor wafer set within the firstright-angled recess of the semiconductor wafer separator; thedownwardly-adjacent wafer separator; and a second semiconductor waferset within the downwardly-adjacent wafer separator.
 10. Thesemiconductor wafer separator of claim 9, wherein a bottom surface ofthe circular ring includes a feature that causes a space to be formedbetween the bottom surface of the circular ring and a top surface of thesecond semiconductor wafer set within the downwardly-adjacent waferseparator.
 11. The semiconductor wafer separator of claim 1, furthercomprising a carrier component extending outward from the outer edge ofthe circular ring.
 12. The semiconductor wafer separator of claim 1,wherein the semiconductor wafer separator comprises polyethylenethermoplastic.
 13. A system comprising: at least two wafer separatorsconfigured to transport at least two semiconductor wafers, each waferseparator of the at least two wafer separators including: a circularring having: an outer edge defining a periphery of the circular ring,and an inner edge defining a central opening of the circular ring; afirst right-angled recess configured for receiving a first semiconductorwafer, wherein the first right-angled recess extends downward from a topsurface of the circular ring; a second right-angled recess configuredfor maintaining a gap between the first semiconductor wafer and thesecond right-angled recess when the first semiconductor wafer is setwithin the first right-angled recess; a first interlock componentdisposed along the top surface of the circular ring and configured toengage an upwardly-adjacent wafer separator; and a second interlockcomponent disposed along a bottom surface of the circular ring andconfigured to engage a downwardly-adjacent wafer separator.
 14. Thesystem of claim 13, wherein the first interlock component is a recessadapted to engage a protruding interlock component of theupwardly-adjacent wafer separator.
 15. The system of claim 13, whereinthe second interlock component is a protrusion adapted to engage arecessing interlock component of the downwardly-adjacent waferseparator.
 16. The system of claim 13, wherein each wafer separatorfurther comprises: a carrier component extending outward from the outeredge of the circular ring.
 17. The system of claim 13, furthercomprising: a first cover disposed above an uppermost wafer separator ofthe at least two wafer separators; a second cover disposed below alowermost wafer separator of the at least two wafer separators; a firstprotective substrate disposed between the first cover and the uppermostwafer separator; and a second protective substrate disposed between thesecond cover and the lowermost wafer separator.
 18. A method comprising:receiving a wafer separator including: a circular ring having: an outeredge defining a periphery of the circular ring, and an inner edgedefining a central opening of the circular ring; a first right-angledrecess extending downward from a top surface of the circular ring; and asecond right-angled recess configured to maintain a gap beneath thesemiconductor wafer when the semiconductor wafer is set within the firstright-angled recess; and placing the semiconductor wafer within thefirst right-angled recess of the wafer separator.
 19. The method ofclaim 18, further comprising: engaging a protrusion on a bottom surfaceof the wafer separator with a recess on a top surface of adownwardly-adjacent wafer separator to secure the wafer separator to thedownwardly-adjacent wafer separator.
 20. The method of claim 18, furthercomprising: engaging a recess on a top surface of the wafer separatorwith a protrusion on a bottom surface of an upwardly-adjacent waferseparator to secure the wafer separator to the upwardly-adjacent waferseparator.
 21. The method of claim 18, further comprising: removing thesemiconductor wafer from the first right-angled recess of the waferseparator using at least one notch of a plurality of notches in thecircular ring.
 22. The method of claim 21, wherein the plurality ofnotches are exposed on the outer edge and the inner edge, and whereinthe plurality of notches are located equidistant around the periphery ofthe circular ring.